Multicycle Operation

It is impractical to require that all MIPS floating-point operations complete in1 clock cycle, or even in 2. Doing so would mean accepting a slow clock, or using enormous amounts of logic in the floating-point units, or both. Instead, the floating-point pipeline will allow for a longer latency for operations. This is easier to grasp if we imagine the floating-point instructions as having the same pipe- line as the integer instructions, with two important changes. First, the EX cycle may be repeated as many times as needed to complete the operation—the number of repetitions can vary for different operations. Second, there may be multiple floating-point functional units. A stall will occur if the instruction to be issued will either cause a structural hazard for the functional unit it uses or cause a data hazard. Let’s assume that there are four separate functional units in our MIPS implementation: 1.  The main integer unit that handles loads and stores, integer ALU operations, and branches 2.  FP and integer multiplier 3.  FP adder that handles FP add, subtract, and conversion 4.  FP and integer divider