1 |
Fundamentals of computer design |
2 |
Measuring and reporting performance |
3 |
Quantitative principles of computer design |
4 |
ISA |
6 |
Pipelining |
5 |
Deign issues ISA |
7 |
Pipeline hazard |
8 |
Implementation |
9 |
Multicycle operation |
10 |
Instruction Level Parallelism |
11 |
Dynamic scheduling |
12 |
Dynamic hardware prediction |
13 |
|
14 |
Multiple Issue |
15 |
Hardware based speculation |
16 |
Limitations of ILP |
17 |
case study |
18 |
Compiler techniques for exposing ILP |
20 |
Static branch prediction |
21 |
Hardware support for exposing more parallelism |
22 |
Hardware vs software speculation mechanism |
23 |
Case study |
24 |
Symmetric shared memory architecture |
25 |
distributed shared memory and directory based
coherence |
26 |
Performance issues |
27 |
Synchronisation issues |
28 |
Models of memory consistency |
29 |
Software and hardware multithreading |
30 |
SMT architecture |
31 |
CMP architecture |
32 |
Case study |
33 |
Cache performance |
34 |
Reducing cache miss penalty |
35 |
Reducing hit time |
36 |
Main memeory and performance |
37 |
Memory Technology |
38 |
Types of storage devices |
39 |
Buses and RAID |
40 |
Reliability, availability and dependability |
41 |
I/O performance |
|
|
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9. Assume that a simple addition of two elements requires a unit time. You are
ReplyDeleterequired to compute the execution time needed to perform the addition of a
40 40 elements array using each of the following arrangements:
(a) A SIMD system having 64 processing elements connected in nearestneighbor
fashion. Consider that each processor has only its local
memory.
(b) A SIMD system having 64 processing elements connected to a shared
memory through an interconnection network. Ignore the communication
time.
(c) A MIMD computer system having 64 independent elements accessing a
shared memory through an interconnection network. Ignore the communication
time.
(d) Repeat (b) and (c) above if the communication time takes two time units.
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