Hardware support for exposing more parallelism

Hardware support for exposing more parallelism Use speculative instructions (Second approach) using a speculative load (sLD) and a speculation check instruction (SPECCK) to completely preserve exception behavior checking for a possible exception Processing the possible exception and complete the load instruction  Conditional or Predicated Instructions •         Most common form is move   •         Other variants –        Conditional loads and stores –        ALPHA, MIPS, SPARC, PowerPC, and P6 all have simple conditional moves –        IA_64 supports full predication for all instructions •         Effect is to eliminating simple branches –        Moves dependence resolution point from early in the pipe (branch resolution) to late in the pipe (register write) à forwarding…is more possible –        Also changes a control dependence into a data dependence Conditional Instruction in Superscalar First slot(Mem)     Second slot (ALU) LW R1,40(R2)                ADD R3, R4, R5                                         ADD R6, R3, R7 BEQZ R10, L    LW R8, 20(R10) LW R9, 0(R8) •         Waste a memory operation slot in the 2nd cycle •         data dependence stall if not taken First slot(Mem)     Second slot (ALU) LW R1,40(R2)                ADD R3, R4, R5 LWC R8,20(R10),R10 ADD R6, R3, R7 BEQZ R10, L    LW R9, 0(R8) Condition Instruction Limitations •         Precise Exceptions –        If an exception happens prior to conditional evaluation, it must be carried through the pipe –        Simple for register accesses but consider a memory protection violation or a page fault •         Long conditional sequences – If-then with a big then body –        If the task to be done is complex, better to evaluate the condition once and then do the big block •         Conditional instructions are most useful when the condition can be evaluated early –        If data dependence in determining the condition à help less •         Wasted resource –        Conditional instructions consume real resources –        Tends to work well in the superscalar case •          Our simple 2-way model è Even if no conditional instruction, other resource is wasted anyway •         Cycle-time or CPI Issues –        Conditional instructions are more complex –        Danger is that they may consume more cycles or a longer cycle time –        Note that the utility is mainly to correct short control flaws •         Hence use may not be for the common case •         Things better not slow down for the real common case to support the uncommon case